46 research outputs found
The complexity of dominating set reconfiguration
Suppose that we are given two dominating sets and of a graph
whose cardinalities are at most a given threshold . Then, we are asked
whether there exists a sequence of dominating sets of between and
such that each dominating set in the sequence is of cardinality at most
and can be obtained from the previous one by either adding or deleting
exactly one vertex. This problem is known to be PSPACE-complete in general. In
this paper, we study the complexity of this decision problem from the viewpoint
of graph classes. We first prove that the problem remains PSPACE-complete even
for planar graphs, bounded bandwidth graphs, split graphs, and bipartite
graphs. We then give a general scheme to construct linear-time algorithms and
show that the problem can be solved in linear time for cographs, trees, and
interval graphs. Furthermore, for these tractable cases, we can obtain a
desired sequence such that the number of additions and deletions is bounded by
, where is the number of vertices in the input graph
Algorithmic aspects of disjunctive domination in graphs
For a graph , a set is called a \emph{disjunctive
dominating set} of if for every vertex , is either
adjacent to a vertex of or has at least two vertices in at distance
from it. The cardinality of a minimum disjunctive dominating set of is
called the \emph{disjunctive domination number} of graph , and is denoted by
. The \textsc{Minimum Disjunctive Domination Problem} (MDDP)
is to find a disjunctive dominating set of cardinality .
Given a positive integer and a graph , the \textsc{Disjunctive
Domination Decision Problem} (DDDP) is to decide whether has a disjunctive
dominating set of cardinality at most . In this article, we first propose a
linear time algorithm for MDDP in proper interval graphs. Next we tighten the
NP-completeness of DDDP by showing that it remains NP-complete even in chordal
graphs. We also propose a -approximation
algorithm for MDDP in general graphs and prove that MDDP can not be
approximated within for any unless NP
DTIME. Finally, we show that MDDP is
APX-complete for bipartite graphs with maximum degree
Parameterized Edge Hamiltonicity
We study the parameterized complexity of the classical Edge Hamiltonian Path
problem and give several fixed-parameter tractability results. First, we settle
an open question of Demaine et al. by showing that Edge Hamiltonian Path is FPT
parameterized by vertex cover, and that it also admits a cubic kernel. We then
show fixed-parameter tractability even for a generalization of the problem to
arbitrary hypergraphs, parameterized by the size of a (supplied) hitting set.
We also consider the problem parameterized by treewidth or clique-width.
Surprisingly, we show that the problem is FPT for both of these standard
parameters, in contrast to its vertex version, which is W-hard for
clique-width. Our technique, which may be of independent interest, relies on a
structural characterization of clique-width in terms of treewidth and complete
bipartite subgraphs due to Gurski and Wanke
Extension of Some Edge Graph Problems: Standard and Parameterized Complexity
Le PDF est une version auteur non publiée.We consider extension variants of some edge optimization problems in graphs containing the classical Edge Cover, Matching, and Edge Dominating Set problems. Given a graph G=(V,E) and an edge set U⊆E, it is asked whether there exists an inclusion-wise minimal (resp., maximal) feasible solution E′ which satisfies a given property, for instance, being an edge dominating set (resp., a matching) and containing the forced edge set U (resp., avoiding any edges from the forbidden edge set E∖U). We present hardness results for these problems, for restricted instances such as bipartite or planar graphs. We counter-balance these negative results with parameterized complexity results. We also consider the price of extension, a natural optimization problem variant of extension problems, leading to some approximation results
Computing strong lower and upper bounds for the integrated multiple-depot vehicle and crew scheduling problem with branch-and-price
In the problem of the title, vehicle and crew schedules are to be determined simultaneously
in order to satisfy a given set of trips over time. The vehicles and the crew are assigned
to depots, and a number of rules have to be observed in the course of constructing feasible schedules.
The main contribution of the paper is a novel mathematical programming formulation which
combines ideas from known models, and an exact solution procedure based on branch-and-price.
The method is tested on benchmark instances from the literature and it provides suboptimal
schedules using limited computational resources
The multi-stripe travelling salesman problem
In the classical Travelling Salesman Problem (TSP), the objective function sums the costs for travelling from one city to the next city along the tour. In the q-stripe TSP with q ≥ 1, the objective function sums the costs for travelling from one city to each of the next q cities along the tour. The resulting q-stripe TSP generalizes the TSP and forms a special case of the quadratic assignment problem. We analyze the computational complexity of the q-stripe TSP for various classes of specially structured distance matrices. We derive NP-hardness results as well as polyomially solvable cases. One of our main results generalizes a well-known theorem of Kalmanson from the classical TSP to the q-stripe TSP
CODE ASSIGNMENT FOR HIDDEN TERMINAL INTERFERENCE AVOIDANCE IN MULTIHOP PACKET RADIO NETWORKS
Hidden terminal interference is caused by the (quasi-) simultaneous transmission of two stations that cannot hear each other, but are both received by the same destination station. This interference lowers the system throughput and increases the average packet delay. Some random access protocols that reduce this interference have been proposed, e.g., BTMA protocol. However, the hidden terminal interference can be totally avoided only by means of code division multiple access (CDMA) schemes. In this paper, we investigate the problem of assigning orthogonal codes to stations so as to eliminate the hidden terminal interference. Since the codes share the fixed channel capacity allocated to the network in the design stage, their number must not exceed a given bound. In this paper, we seek for assignments that minimize the number of codes used. We show that this problem is NP-complete, and thus computationally intractable, even for very restricted but very realistic network topologies. Then, we present optimal algorithms for further restricted topologies, as well as fast suboptimal centralized and distributed heuristic algorithms. The results of extensive simulation set up to derive the average performance of the proposed heuristics on realistic network topologies are presented
A POLYNOMIAL FEASIBILITY TEST FOR PREEMPTIVE PERIODIC SCHEDULING OF UNRELATED PROCESSORS
We consider the problem of preemptive scheduling a set of periodically occurring jobs on a set of unrelated processors, that is, processors having different speeds for different jobs. We assume that each occurrence of a job has to be completely processed before the next occurrence of the same job. We provide a system of linear inequalities for testing the existence of a feasible schedule which can be solved in polynomial time. We then use the solution to this linear system, if any, for constructing a feasible schedule in a straightforward way
A VLSI IMPLEMENTATION OF THE SIMPLEX ALGORITHM
The use of a special-purpose VLSI chip for solving a linear programming problem is presented. The chip is structured as a mesh of trees and is designed to implemented the well-known simplex algorithm. A high degree of parallelism is introduced in each pivot step, which can be carried out in O(log n) time using an m multiplied by m mesh of trees having an O(mn log m log**3 n) area where m-1 and n-1 are the number of constraints and variables, respectively. Two variants of the simplex algorithm are also considered: the two-phase method and the revised one. The proposed chip is intended as a possible basic block for a VLSI operations research machine